The present invention relates in general to the field of electronic testing of semiconductor wafers and chip circuitry using a test probe array, and methods of making same.
Semiconductor chips are typically manufactured en masse in so called wafers. Each wafer is made of a semiconductor material and typically is four to twelve inches in diameter. Each wafer typically contains a plurality of identical chips each connected and adjacent one another, but separated by portions of the wafer called scribe lines. The scribe lines do not contain devices which are required in the finished chips. Generally, the individual chips are separated (or xe2x80x9cdicedxe2x80x9d) from one another for packaging and/or electrical connection to other chips. Prior to the further processing and connection, however, the chips are desirably tested in order to determine which chips are defective so that further expense in processing does not occur on the defective chips. The testing is typically called xe2x80x9cprobing.xe2x80x9d This testing may be accomplished by testing a single chip or multiple chips in defined rows on the wafer, and then repeating the testing operation with other chips or rows. Alternatively, the chips may be separated from one another first and then tested individually. Typically, probe contacts are abutted against (and preferably gently scrubbed or scraped against) respective chip contacts so that the chip circuitry may be tested. The process of testing one chip or a few chips at a time is slow and hence costly. Recently, simultaneous testing of a full undiced wafer has been discussed and is being tried by several manufacturers.
When probing chips or wafers, it has been important to have a planar set of probe contacts so that each probe contact can make simultaneous electrical contact to a respective chip contact. It has also been important to have the contacts on the wafer coplanar. Typically, if the tips of the probe contacts do not lie in approximately the same plane, or if some of the contacts on the wafer are out of plane, more force must be exerted on the back of the probe in an effort to engage all of the probe contacts with the chip contacts. This typically leads to non-uniform forces between the tips of the probe contacts and the wafer contacts. If too much force is placed on any one probe contact, there is a potential to harm the chip contacts. Planarity and a balanced probe contact force is also important in order to have approximately the same ohmic resistance across all of the probe contacts so that the electrical signals have approximately the same level of integrity. Maintaining similar ohmic probe to chip contact resistance is especially important for accurate testing of chips that are designed to be run at high speeds. For these high speed chips, it is also important to control the impedance of the probe tester (resistance, capacitance and inductance) as a whole to maintain the integrity of the electrical signals.
U.S. Pat. No. 4,566,184 discloses a probe card that has a board with an aperture in it. The board has conductive traces on a top surface. A bottom surface of the board has a conductive layer which is used as a ground layer. The conductive traces are connected to electroplated probe contacts that are located below the board aperture and connected to the traces by way of wire bonded connections. The assembly is encapsulated (such as by an acrylic potting compound) in order to hold the probe contacts in place and protect the wire bonds. The wire bonded wires connecting the probe board to the contacts provide an uncontrolled impedance path that will introduce added inductance into the probe system. Also, because of the limitations inherent with such wire bonded connections, it would be difficult to make connections to high density chip contacts and area array chip contacts without substantial fear that the wires would short against each other.
U.S. Pat. Nos. 4,757,256 and 4,837,622 disclose a probe tester that makes use of an array of cantilevered, resilient wires each of which extends from the surface of the probe card downwardly towards the chip contacts. The probe contact array includes an annular frame, and two sets of spaced apart probe wires bonded to the annular frame by a curable resin material. The probes are bonded in alignment position relative to respective connection pads formed on each of the chips on the wafer for individual testing of chips on an undiced wafer. The adjacent probe wires of both sets are substantially parallel with each other, one set of probe wires being spaced apart from the other set. One set of probes is adapted for electrical connection to the first set of traces on the lower surface, and the other set of probes is adapted for electrical connection to the second set of traces on the upper surface of the printed circuit probe card, in all cases by way of the lower surface thereof. This type of probe card has difficulty when the center-to-center distance (xe2x80x9cpitchxe2x80x9d) of the chip contacts becomes fairly small or when the contacts are not located on a periphery of the chip itself. Also, the distended wires may cause excessive scrubbing of the chip contacts and shorting of adjacent probe wires during testing or handling of the probe card.
U.S. Pat. No. 5,613,861 discloses a spring contact probe designed to eliminate the need to create uniform solder bumps or uniform contacting pressure. The spring contacts are formed of a thin metal strip which is in part fixed to a substrate and electrically connected to a contact pad on the substrate. The free portion of the metal strip not fixed to the substrate bends up and away from the substrate because of a stress gradient formed into it. When the contact pad on a device is brought into pressing contact with the free portion of the metal strip, the free portion deforms and provides compliant contact with the contact pad. Since the metal strip is electrically conductive or coated with a conductive material, the contact pad on the substrate is electrically connected to the contact pad on the device via the spring contact.
U.S. Pat. No. 5,177,439 discloses an interface probe card for testing unencapsulated semiconductor devices. The probe card is manufactured from a semiconductor substrate material. A plurality of protrusions is formed in the top surface of the substrate. Each protrusion is coated with a layer of conducting material. The protrusions are patterned to match either a peripheral or an area array of electrode pads on the device to be tested. Conductive interconnects couple each of the plurality of coated protrusions to an external test system. The probe card design disclosed in this patent has the benefit of using semiconductor type equipment for its manufacture but makes a somewhat rigid connection during a probe operation.
U.S. Pat. No. 5,513,430 discloses a method for manufacturing a probe card. A layer of resist is formed on a plating base. The layer of resist is exposed to radiation and developed to provide angled, tapered openings exposing portions of the plating base, such as by using X-ray radiation. An electrically conductive material is electroplated on the exposed portions of the plating base and fills the angled, tapered openings. The layer of resist and portions of the plating base between the electroplated conductive material are removed. The electrically conductive material forms the probe card probes which are angled and tapered. In addition, the compliant probe card probes may be stair-step shaped if more conventional UV radiation is used in defining the tapered openings in the plating base.
U.S. Pat. No. 5,070,297 discloses a wafer level probe tester where all of the chips are tested simultaneously prior to a dicing operation. The disclosed probe tester is created using standard wafer processing techniques to embed active testing and interfacing circuitry in the probe""s base silicon substrate. Each probe tester has a plurality of probe contacts or tips that are electrically connected to the probe tester""s circuitry. In this disclosure, the probe tester may also have memory for storing the probe data after the probe tester has probed a wafer. While the ability to have internal circuitry in the probe tester potentially increases the ability to test the chips in the wafer at higher speeds, it has the drawback of requiring extra processing of the tester""s base substrate. As more and more circuitry is added across the face of the tester""s base substrate, the probe tester encounters the same problems encountered in the field with wafer-scale integration techniques, namely the yield of the circuitry within the base substrate will be adversely affected as more circuitry is added to the base substrate. The problem usually occurs when very high yielding circuitry is used with lower yielding circuitry. The aggregate yield of the resulting circuitry is never any higher than the lowest yielding circuitry, leading to a more expensive process and structure.
Bumped flex test technology has been used by several manufacturers (also known as xe2x80x9cmembrane probe card technologyxe2x80x9d). Test circuits are created on a membrane, such as a thin flexible polymeric substrate or silicon substrate. Typically such test circuits are limited to diameters of approximately 3 inches and incorporate bump contact feature sizes of 50 microns minimum line and space. Such feature sizes are necessary to access the I/O lands of the IC device. Such contact bumps can be as small as 50 microns in both diameter and height. The simplest method of creating the contact bumps is by deforming the metal from the back side by use of a forming die consisting of pins that are located where the contact bumps are to be located. This method works very effectively but is limited in terms of minimum size of the bump that can be produced and in terms of performance because the cavity created during the bump formation can be a source of weakness. In addition, such contact bumps normally must be over plated after the forming process with a suitable contact finish such as gold. This is not only cumbersome but can add to whatever non-planarity that was present in the part initially.
Another method used for creating the bumps, especially micro-bumps or metal contact bumps having dimensions of less than 250 microns across and rising 25 to 100 microns above the surface, is to uniformly plate up the bumps from the surface of the conductor. This has been performed by several manufacturers and is the method of choice for creating uniform contact bumps. These methods for creating a membrane probe card have been seen as either cost prohibitive or have been viewed as impractical for testing of printed circuit boards (xe2x80x9cPCBsxe2x80x9d). This is due perhaps to the intrinsically high cost of the test circuits and the small and delicate nature of the test circuits.
Another membrane probe tester for testing unpackaged chips having flip chip solder balls attached to their contacts is shown in U.S. Pat. No. 5,062,203. The ""203 Patent does not make use of the aforementioned bump contacts because they can deform or damage the flip chip solder balls on the chip""s contacts and typically have a difficult time maintaining contact with the solder ball""s curved surface. Instead, this reference uses a thin film of flexible material having recessed conductive vias so that the tips of each solder ball can be captured therein. Other flex based probe card solutions are disclosed in U.S. Pat. Nos. 5,123,850; 5,225,037; 5,436,568; 5,491,427; 5,500,604; 5,623,213; 5,625,298; 5,239,260.
The technology disclosed in commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,414,298; 5,455,390; 5,518,964; 5,808,874; and 5,525,545; and pending U.S. patent application Ser. No. 09/405,029 entitled, xe2x80x9cMethod and Structures For Electronic Probing Arraysxe2x80x9d, filed on Sep. 24, 1999 is also relevant to the present invention. The disclosures in all such recited commonly assigned patents and patent application are hereby incorporated by reference herein.
Notwithstanding the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable. As previously noted, the process of testing one chip or a few chips at a time is slow and hence costly. It is therefore desirable to provide a test probe for simultaneously testing all of the chips in a wafer, or in other arrays of chips which have a multitude of contacts. By way of example, memory chips arranged in a 5xc3x976 array will have approximately one hundred contacts, while microprocessor chips in a similar array will have approximately five hundred contacts. Due to the very small center-to-center contact distance in these chips, a very high density of contacts is realized. This necessitates the construction of a probe having corresponding center-to-center probe tip dimensions in one-to-one positional relationship with the chip contacts. The ability to test a plurality of chips in, for example, the aforesaid arrays using known parallel test methods, requires that each test probe occupy a minimum of real estate on the wafer card. At the same time, probe density must accommodate the wiring density of each probe to the test computer which will be used during the probing process to determine the existence of defective chips.
As previously discussed, it has been generally important to have a planar set of probe contacts so that each probe contact can make simultaneous electrical contact to a respective chip contact. The typical failure mode of such a probe card is the absence of flexibility to allow the probe contacts to contact the non-planar surfaces of the chip contacts. These circumstances result in a number of inherent problems during the probing process as described hereinabove. The foregoing issues of probe contact density and planarity are addressed by the wafer probe card of the present invention.
In accordance with one embodiment of the invention, there is provided a probe card for testing electronic elements, the probe card comprising a substrate, a layer of dielectric material having a plurality of cavities therein supported on the substrate, a mass of fusible conductive material having a melting temperature below about 125xc2x0 C. disposed in each of the cavities, the dielectric material electrically insulating the masses of fusible conductive material from one another, and a probe tip of conductive material having a melting temperature greater than about 125xc2x0 C. at one common end of each of the masses of fusible conductive material, the layer of dielectric material having a plurality of channels formed therein, whereby each of the mass of fusible conductive material is surrounded by the dielectric material forming a probe contact, each of the probe contacts being separated from an adjacent probe contact by at least one of the channels.
In accordance with one embodiment of the invention, there is provided a probe card for testing electronic elements, the probe card comprising a substrate including electrical circuitry thereon having contacts, a layer of dielectric material having a plurality of cavities therein supported on the substrate, a mass of fusible conductive material having a melting temperature below about 150xc2x0 C. disposed in each of the cavities, each of the masses of fusible conductive material being bonded to one of the contacts, and the dielectric material electrically insulating the masses of fusible conductive material from one another, and a probe tip of conductive material having a melting temperature greater than about 150xc2x0 C. at one common end of each of the masses of fusible conductive material, and the layer of dielectric material having a plurality of channels formed therein, whereby each of the masses of fusible conductive material is surrounded by the dielectric material forming a probe contact, each of the probe contacts being separated from an adjacent probe contact by at least one of the channels.
In accordance with one embodiment of the invention, there is provided a probe card test assembly comprising an electronic element having a plurality of contacts thereon; and a probe card comprising a substrate, a layer of dielectric material having a plurality of cavities therein supported on the substrate, a mass of fusible conductive material having a melting temperature below about 150xc2x0 C. disposed in each of the cavities, and the dielectric material electrically insulating the masses of fusible conductive material from one another, and a probe tip of conductive material having a melting temperature greater than about 150xc2x0 C. at one common end of each of the masses of fusible conductive material, at least one of the probe tips in contact with one of the contacts on said electronic element, and the layer of dielectric material having a plurality of channels formed therein, whereby each of the masses of fusible conductive material is surrounded by the dielectric material forming a probe contact, each of the probe contacts being separated from an adjacent probe contact by at least one of the channels.
In accordance with one embodiment of the invention, there is provided a method of making a probe card comprising forming a plurality of cavities in a sacrificial first substrate, depositing a first metal over the substrate and into the cavities to form a plurality of probe tips, depositing a mass of fusible conductive material over each of the probe tips, providing a substrate having a plurality of contacts on one surface thereof facing the sacrificial substrate, bonding each of the masses of fusible conductive material to a corresponding one of the contacts on the second substrate, providing a dielectric material between the first and second substrates surrounding each of the masses of fusible conductive material to form a dielectric encapsulant layer encapsulating each of the masses of conductive fusible material, removing the sacrificial first substrate, and at least partially separating each the masses of conductive fusible material within said encapsulant layer to form a plurality of individual contact probes each surrounded by the encapsulant layer.
In accordance with one embodiment of the invention, there is provided a method for testing an electronic element using a probe card, the method comprising a probe card having a substrate, a layer of dielectric material having a plurality of cavities therein supported on the substrate, a mass of fusible conductive material having a melting temperature disposed in each of the cavities, and the dielectric material electrically insulating the masses of fusible conductive material from one another, and a probe tip of conductive material having a melting temperature greater than the melting temperature of the mass of fusible conductive material at one common end of each of the masses of fusible conductive material, and the layer of dielectric material having a plurality of channels formed therein, whereby each of the masses of fusible conductive material is surrounded by the dielectric material forming a probe contact, each of the probe contacts being separated from an adjacent probe contact by at least one of the channels; positioning of the probe card opposing an electronic element having a plurality of contacts thereon, at least one of the contacts engaged by one of the probe tips; heating the mass of fusible conductive material to at least the melting temperature of the fusible conductive material, sending signals to the probe card and the electronic element.